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Austin Semiconductor, Inc. 256K X 4 VRAM
256K x 4 DRAM with 512K x 4 SAM
AVAILABLE AS MILITARY SPECIFICATIONS
* SMD 5962-89497 * MIL-STD-883
SMJ44C251B MT42C4256
PIN ASSIGNMENT (Top View)
VRAM
28-Pin DIP (C) (400 MIL)
SC SDQ1 SDQ2 TR\/OE\ DQ1 DQ2 ME\/WE\ NC RAS\ A8 A6 A5 A4 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vss SDQ4 SDQ3 SE\ DQ4 DQ3 DSF CAS\ QSF A0 A1 A2 A3 A7
28-Pin SOJ (DCJ) 28-Pin LCC (EC)
SC SDQ1 SDQ2 TR\/OE\ DQ1 DQ2 ME\/WE\ NC RAS\ A8 A6 A5 A4 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vss SDQ4 SDQ3 SE\ DQ4 DQ3 DSF CAS\ QSF A0 A1 A2 A3 A7
FEATURES
* Class B High-Reliability Processing * DRAM: 262144 Words x 4 Bits SAM: 512 Words x 4 Bits * Single 5-V Power Supply (10% Tolerance) * Dual Port Accessibility-Simultaneous and Asynchronous Access From the DRAM and SAM Ports * Bidirectional-Data-Transfer Function Between the DRAM and the Serial-Data Register * 4 x 4 Block-Write Feature for Fast Area Fill Operations; As Many as Four Memory Address Locations Written per Cycle From an On-Chip Color Register * Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design * Enhanced Page-Mode Operation for Faster Access * CAS-Before-RAS (CBR) and Hidden Refresh Modes * All Inputs/Outputs and Clocks Are TTL Compatible * Long Refresh Period: Every 8 ms (Max) * Up to 33-MHz Uninterrupted Serial-Data Streams * 3-State Serial I/Os Allow Easy Multiplexing of Video-Data Streams * 512 Selectable Serial-Register Starting * Split Serial-Data Register for Simplified Real-Time Register Reload
28-Pin ZIP (CZ)
DSF DQ3 SDQ2 Vss SDQ0 TRG\ DQ1 GND A8 A5 Vcc A3 A1 QSF 1 3 5 7 9 11 13 15 17 19 21 23 25 27 2 4 6 8 10 12 14 16 18 20 22 24 26 28 DQ2 SE\ SDQ3 SC SDQ1 DQ0 W\ RAS\ A8 A4 A7 A2 A0 CAS\
28-Pin FP (F)
SC SDQ1 SDQ2 TR\/OE\ DQ1 DQ2 ME\/WE\ NC RAS\ A8 A6 A5 A4 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vss SDQ4 SDQ3 SE\ DQ4 DQ3 DSF CAS\ QSF A0 A1 A2 A3 A7
OPTIONS
* Timing 100ns, 30ns/27ns 120ns, 35ns/35ns * Package(s) Ceramic SOJ Ceramic DIP (400 mil) Ceramic LCC Ceramic Flat Pack Ceramic ZIP Ceramic LCC
MARKING
-10 -12 MT Prefix DCJ C EC F CZ --SMJ Prefix --JDM HMM --SVM HJM
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PIN NAME PIN NAME (SMJ) (MT) A0 - A8 A0 - A8 CAS\ CAS\ DQ0 - DQ3 DQ1 - DQ4 SE\ SE\ RAS\ RAS\ SC SC SDQ0 - SDQ3 SDQ1 - SDQ4 TRG\ TR\ /OE\ W\ ME\ /WE\ DSF DSF QSF QSF Vcc Vcc Vss Vss GND NC
DESCRIPTION Address Inputs Column Enable DRAM Data In-Out/Write-Mask Bit Serial Enable Row Enable Serial Data Clock Serial Data In-Out Transfer Register/Q Output Enable Write-Mask Select/Write Enable Special Function Select Split-Register Activity Status 5V Supply Ground Ground (Important: Not Connected to internal Vss, Pin should be left open or tied to ground.
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DESCRIPTION
The SMJ44C251B/MT42C4256 multiport video RAM is a high-speed, dual-ported memory device. It consists of a dynamic random-access memory (DRAM) organized as 262144 words of 4 bits each interfaced to a serial-data register or serialaccess memory (SAM) organized as 512 words of 4 bits each. The SMJ44C251B/MT42C4256 supports three types of operation: random access to and from the DRAM, serial access to and from the serial register, and bidirectional transfer of data between any row in the DRAM and the serial register. Except during transfer operations, the SMJ44C251B/MT42C4256 can be accessed simultaneously and asynchronously from the DRAM and SAM ports. During a transfer operation, the 512 columns of the DRAM are connected to the 512 positions in the serial data register. The 512 x 4-bit serial-data register can be loaded from the memory row (transfer read), or the contents of the 512 x 4-bit serial-data register can be written to the memory row (transfer write). The SMJ44C251B/MT42C4256 is equipped with several features designed to provide higher system-level bandwidth and to simplify design integration on both the DRAM and SAM ports. On the DRAM port, greater pixel draw rates can be achieved by the device's 4 x 4 block-write mode. The blockwrite mode allows four bits of data (present in an on-chip colordata register) to be written to any combination of four adjacent column-address locations. As many as 16 bits of data can be written to memory during each CAS cycle time. Also on the DRAM port, a write mask or a write-per-bit feature allows masking any combination of the four input/outputs on any write cycle. The persistent write-per-bit feature uses a mask register that, once loaded, can be used on subsequent write cycles. The mask register eliminates having to provide mask data on every mask-write cycle. The SMJ44C251B/MT42C4256 offers a split-register transfer read (DRAM to SAM) feature for the serial tester (SAM port). This feature enables real-time register reload implementation for truly continuous serial data streams without critical timing requirements. The register is divided into a high
SMJ44C251B MT42C4256
VRAM
half and a low half. While one half is being read out of the SAM port, the other half can be loaded from the memory array. For applications not requiring real-time register reload (for example, reloads done during CRT retrace periods), the single-register mode of operation is retained to simplify design. The SAM can also be configured in input mode, accepting serial data from an external device. Once the serial register within the SAM is loaded, its contents can be transferred to the corresponding column positions in any row in memory in a single memory cycle. The SAM port is designed for maximum performance. Data can be input to or accessed from the SAM at serial rates up to 33 MHz. During the split-register mode of operation, internal circuitry detects when the last bit position is accessed from the active half of the register and immediately transfers control to the opposite half. A separate output, QSF, is included to indicate which half of the serial register is active at any given time in the split-register mode. All inputs, outputs, and clock signals on the SMJ44C251B/ MT42C4256 are compatible with Series 54 TTL devices. All address lines and data-in lines are latched on-chip to simplify system design. All data-out lines are unlatched to allow greater system flexibility. Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. The time for row-address setup, row-address hold, and address multiplex is eliminated, and a memory cycle time reduction of up to 3x can be achieved, compared to minimum RAS cycle times. The maximum number of columns that can be accessed is determined by the maximum RAS low time and page-mode cycle time used. The SMJ44C251B/MT42C4256 allows a full page (512 cycles) of information to be accessed in read, write, or read-modify-write mode during a single RAS-low period using relatively conservative page-mode cycle times. The SMJ44C251B/MT42C4256 employs state-of-the-art technology for very high performance combined with improved reliability.
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Austin Semiconductor, Inc. FUNCTIONAL BLOCK DIAGRAM
SMJ44C251B MT42C4256
VRAM
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
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Austin Semiconductor, Inc. FUNCTION TABLE
RAS\ FALL FUNCTION CAS\ CBR Refresh Register-to-memory transfer (transfer write) Alternate transfer write (independent of SE\) Serial-write-mode enable (pseudo-transfer write) Memory-to-register transfer (transfer read) Split-register-transfer read (must reload tap) Load and use write mask, Write data to DRAM Load and use write mask, Block write to DRAM Persistent write-per-bit, Write data to DRAM Persistent write-per-bit, Block write to DRAM Normal DRAM read/write (nonmasked) Block write to DRAM (nonmasked) Load write mask Load color register L H H H H H H H H H H H H H TRG\ X L L L L L L H H H H H H H W\ X L L L H H L L L L H H H H
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SMJ44C251B MT42C4256
CAS\ FALL
VRAM
ADDRESS RAS\ CAS\
DQ0 - DQ3 RAS\ CAS\ W\ X X X X X X X DQ Mask DQ Mask X X X X X X X X X X X Valid Data Col Mask Valid Data Col Mask Valid Data Col Mask DQ Mask Color Data
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TYPE R T T T T T R R R R R R R R
3
DSF X X H L L H L L H H L L H H
SE\ X L X H X X X X X X X X X X
DSF X X X X X X L H L H L H L H
X X Row Tap Addr Point Row Tap Addr Point Refresh Tap Addr Point Row Tap Addr Point Row Tap Addr Point Row Col Addr Addr Row Blk Addr Addr A2-A8 Row Col Addr Addr Row Blk Addr A2-A8 Addr Row Col Addr Addr Row Blk Addr A2-A8 Addr Refresh X Addr Refresh X Addr
NOTES:
1. In persistent write-per-bit function, W\ must be high during the refresh cycle. 2. DQ0 - DQ3 are latched on the later of W\ or CAS\ falling edge. Col Mask = H: Write to address/column location enabled. DQ Mask = H: Write to I/O enabled. 3. R = random access operation, T = transfer operation.
LEGEND
H = HIGH L = LOW X = Don't Care
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PIN A0 - A8 CAS\ DQi DSF RAS\ SE\ SC SDQ TRG\ W\ QSF NC/GND Vcc Vss Make no external connection or tie to system Vss 5V supply (typical) Device ground DRAM Row, column address Column enable, output enable DRAM data I/O, write mask bits Block-write enable Persistent write-per-bit enable Color-register load enable Row enable TRANSFER Row, tap address Tap-address strobe Split-register enable Alternative write-transfer enable Row enable Serial-in mode enable
SMJ44C251B MT42C4256
SAM
VRAM
DETAILED SIGNAL DESCRIPTION VS. OPERATIONAL MODE
Serial enable Serial clock Serial-data I/O
Q output enable Write enable, write-per-bit select
Transfer enable Transfer-write enable Split register Active status
OPERATION
Depending on the type of operation chosen, the signals of the SMJ44C251B/MT42C4256 perform different functions. The "Detailed Signal Description vs. Operational Mode" table summarizes the signal descriptions and the operational modes they control. The SMJ44C251B/MT42C4256 has three kinds of operations: random-access operations typical of a DRAM, transfer operations from memory arrays to the SAM, and serialaccess operations through the SAM port. The signals used to control these operations are described here, followed by discussions of the operations themselves. ADDRESS (A0-A8) For DRAM operation, 18 address bits are required to decode one of the 262144 storage cell locations. Nine rowaddress bits are set up on A0-A8 and latched onto the chip on the falling edge of RAS\. Nine column-address bits are set up on A0-A8 and latched onto the chip on the falling edge of CAS\. All addresses must be stable on or before the falling edges of RAS\ and CAS\. During the transfer operation, the states of A0-A8 are latched on the falling edge of RAS\ to select one of the 512 rows where the transfer occurs. To select one of 512 tap points (starting positions) for the serial-data input or output, the appropriate 9-bit column address (A0-A8) must be valid when CAS\ falls.
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ROW-ADDRESS STROBE (RAS\) RAS\ is similar to a chip enable because all DRAM cycles and transfer cycles are initiated by the falling edge of RAS\. RAS\ is a control input that latches the states of row address, W\, TRG\, SE\, CAS\, and DSF onto the chip to invoke DRAM and transfer functions. COLUMN-ADDRESS STROBE (CAS\) CAS\ is a control input that latches the states of column address and DSF to control DRAM and transfer functions. When CAS\ is brought low during a transfer cycle, it latches the new tap point for the serial-data input or output. CAS\ also acts as an output enable for the DRAM outputs DQ0-DQ3. OUTPUT ENABLE/TRANSFER SELECT (TRG\) TRG\ selects either DRAM or transfer operation as RAS\ falls. For DRAM operation, TRG\ must be held high as RAS\ falls. During DRAM operation, TRG\ functions as an output enable for the DRAM outputs DQ0-DQ3. For transfer operation, TRG\ must be brought low before RAS\ falls. WRITE-MASK SELECT, WRITE ENABLE (W\) In DRAM operation, W\ enables data to be written to the DRAM. W\ is also used to select the DRAM write-per-bit mode. Holding W\ low on the falling edge of RAS\ invokes the writeper-bit operation. The SMJ44C251B/MT42C4256 supports both the normal write-per-bit mode and the persistent write-per-bit mode. CONTINUED
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WRITE-MASK SELECT, WRITE ENABLE (W\) (continued) For transfer operation, W\ selects either a read-transfer operation (DRAM to SAM) or a write-transfer operation (SAM to DRAM). During a transfer cycle, if W is high when RAS\ falls, a read transfer occurs; if W is low, a write transfer occurs. SPECIAL FUNCTION SELECT (DSF) DSF is latched on the falling edge of RAS\ or CAS\, similar to an address. DSF determines which of the following functions are invoked on a particular cycle: * Persistent write-per-bit * Block write * Split-register transfer read * Mask-register load for the persistent write-per-bit mode * Color-register load for the block-write mode DRAM DATA I/O, WRITE-MASK DATA (DQ0-DQ3) DRAM data is written via DQ terminals during a write or read-modify-write cycle. In an early-write cycle, W\ is brought low prior to CAS\ and the data is strobed in by CAS\ with data setup and hold times referenced to this signal. In a delayedwrite or read-modify-write cycle, W\ is brought low after CAS\ and the data is strobed in by W\ with data setup and hold times referenced to this signal. The 3-state DQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of two Series 54 TTL loads. Data out is the same polarity as data in. The outputs are in the high-impedance (floating) state as long as CAS\ and TRG\ are held high. Data does not appear at the outputs until both CAS\ and TRG\ are brought low. Once the outputs are valid, they remain valid while CAS\ and TRG\ are low. CAS\ or TRG\ going high returns the outputs to the high-impedance state. In a register-transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle. The write-per-bit mask is latched into the device via the random DQ terminals by the falling edge of RAS\. This mask selects which of the four random I/Os are written. SERIAL DATA I/O (SDQ0-SDQ3) Serial inputs and serial outputs share common I/O terminals. Serial-input or serial-output mode is determined by the previous transfer cycle. If the previous transfer cycle was a read transfer, the data register is in serial-output mode. While in
SMJ44C251B MT42C4256
VRAM
serial-output mode, data in SAM is accessed from the least significant bit to the most significant bit. The data registers operate modulo 512; so after bit 511 is accessed, the next bits to be accessed are 00, 01, 02, etc. If the previous transfer cycle was either a write transfer or a pseudo transfer, the data register is in serial-input mode and signal data can be input to the register. SERIAL CLOCK (SC) Serial data is accessed in or out of the data register on the rising edge of SC. The SMJ44C251B/MT42C4256 is designed to work with a wide range of clock-duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static. There is also no minimum SC clock operating frequency. SERIAL ENABLE (SE\) During serial-access operations SE\ is used as an enable/ disable for SDQ in both the input and output modes. If SE\ is held as RAS\ falls during a write-transfer cycle, a pseudotransfer write occurs. There is no actual transfer, but the data register switches from the output mode to the input mode. NO CONNECT/GROUND (NC/GND) NC/GND is reserved for the manufacturer's test operation. It is an input and should be tied to system ground or left floating for proper device operation. SPECIAL FUNCTION OUTPUT (QSF) During split-register operation the QSF output indicates which half of the SAM is being accessed. When QSF is low, the serial-address pointer is accessing the lower (least significant) 256 bits of SAM. When QSF is high, the serial-address pointer is accessing the higher (most significant) 256 bits of SAM. QSF changes state upon crossing the boundary between the two SAM halves in the split-register mode. During normal transfer operations QSF changes state upon completing a transfer cycle. This state is determined by the tap point being loaded during the transfer cycle. POWER UP To achieve proper device operation, an initial pause of 200ms is required after power-up, followed by a minimum of eight RAS\ cycles or eight CBR cycles, a memory-to-register transfer cycle, and two SC cycles.
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Austin Semiconductor, Inc. RANDOM-ACCESS-OPERATION FUNCTIONS
RAS\ FALL FUNCTION CAS\ CBR Refresh Load and use write mask, Write data to DRAM Load and use write mask, Block write to DRAM Persistent write-per-bit, Write data to DRAM Persistent write-per-bit, Block write to DRAM Normal DRAM read/write (nonmasked) Block write to DRAM (nonmasked) Load write mask Load color register L H H H H H H H H TRG\ X H H H H H H H H W\ X L L L L H H H H
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SMJ44C251B MT42C4256
CAS\ FALL ADDRESS RAS\ CAS\ DQ0 - DQ3 RAS\ CAS\ W\ X X DQ Valid Mask Data DQ Col Mask Mask Valid X Data Col X Mask Valid X Data Col X Mask DQ X Mask Color X Data
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VRAM
DSF X L L H H L L H H
SE\ X X X X X X X X X
DSF X L H L H L H L H
X X Row Col Addr Addr Row Blk Addr Addr A2-A8 Row Col Addr Addr Row Blk Addr Addr A2-A8 Row Col Addr Addr Row Blk Addr Addr A2-A8 Refresh X Addr Refresh X Addr
NOTES:
1. In persistent write-per-bit function, W must be high during the refresh cycle. 2. DQ0-DQ3 are latched on the later of W or CAS falling edge. Col Mask = H: Write to address/column location enabled. DQ Mask = H: Write to I/O enabled
LEGEND:
H = High L = Low X = Don't care
RANDOM-ACCESS OPERATION
The random-access operation functions are summarized in the "Random-Access-Operation Function" table and described in the following sections.
row-address hold time has been satisfied, usually well in advance of the falling edge of CAS\. In this case, data can be obtained after ta(C) max (access time from CAS low), if ta(CA) max (access time from column address) has been satisfied.
ENHANCED PAGE-MODE
Enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. This mode eliminates the time required for row address setup-and-hold and address multiplex. The maximum RAS\ low time and the CAS\ page cycle time used determine the number of columns that can be accessed. Unlike conventional page-mode operation, the enhanced page mode allows the SMJ44C251B/MT42C4256 to operate at a higher data bandwidth. Data retrieval begins as soon as the column address is valid rather than when CAS\ transitions low. A valid column address can be presented immediately after
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REFRESH
There are three types of refresh available on the SMJ44C251B/MT42C4256: RAS\-only refresh, CBR refresh, and hidden refresh.
RAS\-ONLY REFRESH
A refresh operation must be performed to each row at least once every 8 ms to retain data. Unless CAS\ is applied, the output buffers are in the high-impedance state, so the RAS\only refresh sequence avoids any output during refresh. Externally generated addresses must be supplied during RAS-only refresh. Strobing each of the 512 row addresses with RAS causes (continued)
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RAS\-ONLY REFRESH (continued)
all bits in each row to be refreshed. CAS\ can remain high (inactive) for this refresh sequence to conserve power.
SMJ44C251B MT42C4256
VRAM
BLOCK WRITE
The block-write mode allows data (present in an on-chip color register) to be written into four consecutive column-address locations. The 4-bit color register is loaded by the color-register-load cycle. Both write-per-bit modes can be applied in the block-write cycle. The block-write mode also offers the 4 x 4 column-mask capability.
CAS\-BEFORE-RAS\ (CBR) REFRESH
CBR refresh is accomplished by bringing CAS\ low earlier than RAS\. The external row address is ignored and the refresh row address is generated internally when using CBR refresh. Other cycles can be performed in between CBR cycles without disturbing the internal address generation.
LOAD COLOR REGISTER
The load-color-register cycle is performed using normal DRAM write-cycle timing except that DSF is held high on the falling edges of RAS\ and CAS\. A 4-bit code is input to the color register via the random I/O terminals and latched on the later of the falling edge of CAS\ or W\. After the color register is loaded, it retains data until power is lost or until another loadcolor-register cycle is executed.
HIDDEN REFRESH
A hidden refresh is accomplished by holding CAS\ low in the DRAM-read cycle and cycling RAS\. The output data of the DRAM-read cycle remains valid while the refresh is being carried out. Like the CBR refresh, the refreshed row addresses are generated internally during the hidden refresh.
BLOCK WRITE CYCLE WRITE-PER-BIT
The write-per-bit feature allows masking of any combination of the four DQs on any write cycle (see Figure 1). The write-per-bit operation is invoked only when W\ is held low on the falling edge of RAS\. If W\ is held high on the falling edge of RAS\, write-per-bit is not enabled and the write operation is performed to all four DQs. The SMJ44C251B/ MT42C4256 offers two write-per-bit modes: the nonpersistent write-per-bit mode and the persistent write-per-bit mode. After the color register is loaded, the block-write cycle can begin as a normal DRAM write cycle with DSF held high on the falling edge of CAS\ (see Figures 2, 3, and 4). When the blockwrite cycle is invoked, each data bit in the 4-bit color register is written to selected bits of the four adjacent columns of the corresponding random I/O. During block-write cycles, only the seven most significant column addresses (A2-A8) are latched on the falling edge of CAS\. The two least significant addresses (A0-A1) are replaced by four DQ bits (DQ0-DQ3), which are also latched on the later of the falling edge of CAS\ or W\. These four bits are used as a column mask, and they indicate which of the four column-address locations addressed by A2-A8 are written with the contents of the color register during the block-write cycle. DQ0 enables a write to column-address A1 = 0 (low), A0 = 0 (low); DQ1 enables a write to column-address A1 = 0 (low), A0 = 1 (high); DQ2 enables a write to column-address A1 = 1 (high), A0 = 0 (low); DQ3 enables a write to column-address A1 = 1 (high), A0 = 1 (high). A high logic level enables a write, and a low logic level disables the write. A maximum of 16 bits (4 x 4) can be written to memory during each CAS\ cycle in the blockwrite mode.
NONPERSISTENT WRITE-PER-BIT
When DSF is low on the falling edge of RAS\, the write mask is reloaded. A 4-bit code (the write-per-bit mask) is input to the device via the random DQ terminals and latched on the falling edge of RAS\. The write-per-bit mask selects which of the four random I/Os are written and which are not. After RAS\ has latched the on-chip write-per-bit mask, input data is driven onto the DQ terminals and is latched on the later falling edge of CAS\ or W\. When a data low is strobed into a particular I/O on the falling edge of RAS\, data is not written to that I/O. When a data high is strobed into a particular I/O on the falling edge of RAS\, data is written to that I/O.
PERSISTENT WRITE-PER-BIT
When DSF is high on the falling edge of RAS\, the writeper-bit mask is not reloaded: it retains the value stored during the last write-per-bit mask reload. This mode of operation is known as persistent write-per-bit because the write-per-bit mask is persistent over an arbitrary number of write cycles. The writeper-bit mask reload can be done during the nonpersistent writeper-bit cycle or by the mask-register-load cycle.
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SMJ44C251B MT42C4256
VRAM
FIGURE 1: EXAMPLE OF WRITE-PER-BIT OPERATIONS
DQ Mask = H: Write to I/O enable = L: Write to I/O disable
FIGURE 2: EXAMPLE BLOCK-WRITE DIAGRAM OPERATIONS
NOTES:
* W\ must be low during the block-write cycle. DQ0-DQ3 are latched on the later of W\ or CAS\ falling edge except in block 6 (see legend).
LEGEND:
1. 2. 3. 4. 5. 6. Refresh address Row address Block address (A2 -A8) Color-register data Column-mask data DQ-mask data. DQ0-DQ3 are latched on the falling edge of RAS\.
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SMJ44C251B MT42C4256
VRAM
FIGURE 3: BLOCK-WRITE CIRCUIT BLOCK DIAGRAM
FIGURE 4: EXAMPLE OF BLOCK WRITE OPERATION WITH DQ MASK AND ADDRESS MASK
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TRANSFER OPERATION
Transfer operations between the memory arrays (DRAM) and the data registers (SAM) are invoked by bringing TRG\ low before RAS\ falls. The states of W\, SE\, and DSF, which are also latched on the falling edge of RAS\, determine which transfer operation is invoked. Figure 5 shows an overview of data flow between the random and the serial interfaces. As shown in the "Transfer-Operation Functions" table, the SMJ44C251B/MT42C4256 supports five basic modes of transfer operation: * Register-to-memory transfer (normal write transfer, SAM to DRAM) * Alternate-write transfer (independent of the state of SE\)
SMJ44C251B MT42C4256
VRAM
* Memory-to-register transfer (pseudo-transfer write).
Switches serial port from serial-out mode to serial-in mode. No actual data transfer takes place between the DRAM and the SAM. * Memory-to-register transfer (normal-read transfer, transfer entire contents of DRAM row to SAM) * Split-register-read transfer (divides the SAM into a low and a high half. Only one half is transferred to the SAM while the other half is read from the serial I/O port.)
FIGURE 5: BLOCK DIAGRAM SHOWING ONE RANDOM AND ONE SERIAL-I/O INTERFACE
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Austin Semiconductor, Inc. TRANSFER-OPERATION FUNCTIONS
RAS\ FALL FUNCTION CAS\ Register-to-memory transfer (normal write transfer) Alternate-write transfer (independent of SE\) Serial-write-mode enable (pseudo-transfer write) Memory-to-register transfer (normal read transfer) Split-register-read transfer (must reload tap) H H H H H TRG\ L L L L L W\ L L L H H DSF X H L L H SE\ L X H X X CAS\ FALL DSF X X X X X
SMJ44C251B MT42C4256
ADDRESS RAS\ Row Addr Row Addr Refresh Addr Row Addr Row Addr CAS\ Tap Point Tap Point Tap Point Tap Point Tap Point DQ0 - DQ3 RAS\ X X X X X CAS\ W\ X X X X X
VRAM
LEGEND:
H = High L = Low X = Don't Care
WRITE TRANSFER
All write-transfer cycles (except the pseudo write transfer) transfer the entire content of SAM to the selected row in the DRAM. To invoke a write-transfer cycle, W\ must be low when RAS\ falls. There are three possible write-transfer operations: normal-write transfer, alternate-write transfer, and pseudo-write transfer. All write-transfer cycles switch the serial port to the serial-in mode.
PSEUDO-WRITE TRANSFER (write-mode control) (refer to Figure 28)
To invoke the pseudo-write transfer (write-mode control cycle), SE\ is brought high and latched at the falling edge of RAS\. The pseudo-write transfer does not actually invoke any data transfer but switches the mode of the serial port from the serial-out (read) mode to the serial-in (write) mode. Before serial data can be clocked into the serial port via the SDQ terminals and the SC input, the SDQ terminals must be switched into input mode. Because the transfer does not occur during the pseudo-transfer write, the row address (A0-A8) is in the don't care state and the column address (A0-A8), which is latched on the falling edge of CAS\, selects one of the 512 tap points in the SAM that are available for the next serial input.
NORMAL-WRITE TRANSFER (SAM-to-DRAM transfer)
A normal-write transfer cycle loads the contents of the serial-data register to a selected row in the memory array. TRG\, W\, and SE\ are brought low and latched at the falling edge of RAS\. Nine row-address bits (A0-A8) are also latched at the falling edge of RAS\ to select one of the 512 rows available as the destination of the data transfer. The nine column-address bits (A0-A8) are latched at the falling edge of CAS\ to select one of the 512 tap points in SAM that are available for the next serial input. During a write-transfer operation before RAS\ falls, the serial-input operation must be suspended after a minimum delay of td(SCRL) but can be resumed after a minimum delay of td(RHSC) after RAS goes high (see Figure 6).
READ TRANSFER (DRAM-to-SAM transfer) (refer to Figure 7)
During a read-transfer cycle, data from the selected row in DRAM is transferred to SAM. There are two read-transfer operations: normal-read transfer and split-register-read transfer.
NORMAL-READ TRANSFER (refer to Figure 7)
The normal-read-transfer operation loads data from a selected row in DRAM into SAM. TRG\ is brought low and latched at the falling edge of RAS\. Nine row-address bits (A0-A8) are also latched at the falling edge of RAS\ to select one of the 512 rows available for transfer. The nine column(continued)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
ALTERNATE-WRITE TRANSFER (refer to Figure 30)
When DSF is brought high and latched at the falling edge of RAS\ in the normal-write-transfer cycle, the alternate-write transfer occurs.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
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Austin Semiconductor, Inc.
NORMAL-READ TRANSFER (refer to Figure 7)
address bits (A0- A8) are latched at the falling edge of CAS\ to select one of the SAM's 512 available tap points where the serial data is read out.
SMJ44C251B MT42C4256
VRAM
A normal-read transfer can be performed in three ways: early-load read transfer, real-time or midline-load read transfer, and late-load read transfer. Each of these offers the flexibility of controlling the TRG\ trailing edge in the read-transfer cycle (see Figure 7).
FIGURE 6: NORMAL-WRITE-TRANSFER-CYCLE TIMING
FIGURE 7: NORMAL-READ-TRANSFER TIMINGS
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
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13
Austin Semiconductor, Inc.
SPLIT-REGISTER-READ TRANSFER
In split-register-read-transfer operation, the serial-data register is split into halves. The low half contains bits 0-255, and the high half contains 256-511. While one half is being read out of the SAM port, the other half can be loaded from the memory array. To invoke a split-register read-transfer cycle, DSF is brought high, TRG\ is brought low, and both are latched at the falling edge of RAS\. Nine row-address bits (A0-A8) are also latched at the falling edge of RAS\ to select one of the 512 rows available for the transfer. The nine column-address bits (A0-A8) are latched at the falling edge of CAS\, where address bits A0 -A7 select one of the 255 tap points in the specified half of SAM and address bit A8 selects which half is to be transferred. If A8 is a logic low, the low half is transferred. If A8 is a logic high, the high half is transferred. SAM locations 255 and 511 cannot be used as tap points.
SMJ44C251B MT42C4256
VRAM
A normal-read transfer must precede the split-register-read transfer to ensure proper operation. After the normal-readtransfer cycle, the first split-register read transfer can follow immediately without any minimum SC requirement. However, there is a minimum requirement of a rising edge of SC between split-register read-transfer cycles. QSF indicates which half of the SAM is being accessed during serial-access operation. When QSF is low, the serialaddress pointer is accessing the lower (least significant) 256 bits of the SAM. When QSF is high, the pointer is accessing the higher (most significant) 256 bits of the SAM. QSF changes state upon completing a normal-read-transfer cycle. The tap point loaded during the current transfer cycle determines the state of QSF. In split-register read-transfer mode, QSF changes state when a boundary between the two register halves is reached (see Figure 8 and Figure 9).
FIGURE 8: EXAMPLE OF A SPLIT-REGISTER READ-TRANSFER CYCLE AFTER A NORMAL READ-TRANSFER CYCLE
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
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14
Austin Semiconductor, Inc. FIGURE 9: A SPLIT-REGISTER READ-TRANSFER CYCLE AFTER A SPLIT-REGISTER READ-TRANSFER CYCLE
SMJ44C251B MT42C4256
VRAM
SERIAL-ACCESS OPERATION The serial-read and serial-write operations can be performed through the SAM port simultaneously and asynchronously with DRAM operations except during transfer operations. The preceding transfer operation determines the input or output state of the SAM port. If the preceding transfer operation is a read-transfer operation, the SAM port is in the output mode. If
the preceding transfer operation is a write- or pseudo-writetransfer operation, the SAM port is in the input mode. Serial data can be read out of or written into SAM by clocking SC starting at the tap point loaded by the preceding transfer cycle, proceeding sequentially to the most significant bit (bit 511), then wrapping around to the least significant bit (bit 0) (see Figure 10).
FIGURE 10: SERIAL POINTER DIRECTION FOR SERIAL READ/WRITE
For split-register read-transfer operation, serial data can be read out from the active half of SAM by clocking SC starting at the tap point loaded by the preceding split-register-transfer cycle, then proceeding sequentially to the most significant bit of the half, bit 255 or bit 511. If there is a split-register-read transfer to
the inactive half during this period, the serial pointer points next to the tap-point location loaded by that split register (see Figure 11, Case I). If there is no split-register read transfer to the inactive half during this period, the serial pointer points next to bit 256 or bit 0, respectively (see Figure 11, Case II).
FIGURE 11: SERIAL POINTER FOR SPLIT-REGISTER READ
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
15
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Supply voltage range, VCC1.................................................-1V to 7V Voltage range on any pin1..................................................-1V to 7V Short-circuit output current.......................................................50mA Power dissipation............................................................................1W Operating free-air temperature range, TA...................-55C to 125C Storage temperature range, TSTG.................................-65C to 150C NOTE:
1. All voltage values are with respect to Vss.
SMJ44C251B MT42C4256
VRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
SYM VCC VSS VIH VIL TA TC PARAMETER Supply Voltage Supply Voltage High-level input voltage Low-level input voltage** Operating free-air temperature Operating case temperature 2.9 -1 -55 MIN 4.5 NOM 5 0 6.5 0.6 125 125 MAX 5.5 UNIT V V V V C C
NOTE:
**The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
16
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGES AND OPERATING FREE-AIR TEMPERATURE (UNLESS OTHERWISE NOTED)
PARAMETER High-level output voltage Low-level output voltage Input leakage current Output leakage current
2 1
SYM VOH VOL II IO
CONDITIONS IOH = -5mA IOL = 4.2mA VCC = 5V, VI = 0V to 5.8V, All others open VCC = 5.5V, VO = 0V to VCC
MIN 2.4
MAX
UNIT V
0.4 10 10
V A A
-10 PARAMETER Operating current Operating current Standby current Standby current RAS\-only refresh current RAS\-only refresh current Page-mode current Page-mode current CAS\-before-RAS\ current CAS\-before-RAS\ current Data-transfer current Data-transfer current
NOTES:
3
-12 MIN MAX UNITS 90 100 15 35 90 100 60 65 80 100 90 100 mA mA mA mA mA mA mA mA mA mA mA mA
SYM ICC1 ICC1A ICC2 ICC2A ICC3 ICC3A ICC4 ICC4A ICC5 ICC5A ICC6 ICC6A
CONDITIONS tc(rd) and tc(W) = MIN tc(SC) = MIN All clocks = VCC tc(SC) = MIN tc(rd) and tc(W) = MIN tc(SC) = MIN tc(P) = MIN tc(SC) = MIN tc(rd) and tc(W) = MIN tc(SC) = MIN tc(rd) and tc(W) = MIN tc(SC) = MIN
SAM PORT Standby Active Standby Active Standby Active Standby Active Standby Active Standby Active
MIN MAX 100 110 15 35 100 110 65 70 90 110 100 110
1. The SMJ44C251B may exhibit simultaneous switching noise as described in the Texas Instruments Advanced CMOS Logic Designer's Handbook. This phenomenon is exhibited on the DQ terminals when the SDQ terminals are switched and on the SDQ terminals when the DQ terminals are switched. This may cause VOL and VOH to exceed the data-book limit for a short period of time, depending upon output loading and temperature. Care should be taken to provide proper termination, decoupling, and layout of the device to minimize simultaneous switching effects. 2. SE\ is disabled for SDQ output leakage tests. 3. ICC (standby) denotes that the SAM port is inactive (standby) and the DRAM port is active (except for ICC2). ICCA (active) denotes that the SAM port is active and the DRAM port is active (except for ICC2). ICC is measured with no load on DQ or SDQ. 4. For conditions shown as MIN/ MAX, use the appropriate value specified in the timing requirements.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
17
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
CAPACITANCE OVER RECOMMENDED RANGES OF SUPPLY VOLTAGES AND OPERATING FREE-AIR TEMPERATURE, f = 1MHz1
PARAMETER Input capacitance, A0 - A8 Input capacitance, CAS\ and RAS\ Output capacitance, SDQs and DQs Output capacitance, SQSF SYM Ci(A) Ci(RC) Co(O) Co(QSF) MIN MAX 7 7 9 9 UNIT pF pF pF pF
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGES AND OPERATING FREE-AIR TEMPERA-10 -12 TURE2
PARAMETER Access time from CAS\ Access time from column address Access time from CAS\ high Access time from RAS\ Access time of DQ0 - DQ3 from TRG\ low Access time of SDQ0 - SDQ3 from SC high Access time of SDQ0 - SDQ3 from SE\ low Disable time, random output from CAS\ high Disable time, random output from TRG\ high Disable time, random output from SE\ high
3 3
SYM/ALT. SYM ta(C) /tCAC ta(CA)/tCAA ta(CP) /tCPA ta(R) /tRAC ta(G) /tOEA t a(SQ) /tSCA ta(SE) /tSEA tdis(CH) /tOFF tdis(G) /tOEZ tdis(SE) /tSEZ
CONDITIONS
4
MIN
MAX 25 50 55 100 25
MIN
MAX 30 60 65 120 30 35 25
UNIT ns ns ns ns ns ns ns ns ns ns
td(RLCL) = MAX td(RLCL) = MAX td(RLCL) = MAX td(RLCL) = MAX
CL = 30pF CL = 30pF CL = 100pF CL = 100pF CL = 30pF 0 0 0
30 20 20 20 20 0 0 0
20 20 20
3
NOTES:
1. Capacitance is sampled only at initial design and after any major change. Samples are tested at 0 V and 25C with a 1-MHz signal applied to the terminal under test. All other terminals are open. 2. Switching times assume CL = 100 pF unless otherwise noted (see Figure 12). 3. tdis(CH), tdis(G), and tdis(SE) are specified when the output is no longer driven. 4. For conditions shown as MIN/ MAX, use the appropriate value specified in the timing requirements.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
18
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGES AND OPERATING FREE-AIR TEMPERATURE1
-10 PARAMETER Cycle time, read
2 2 2 2 2
-12 MAX MIN 220 220 290 70 125 220 220 35 30 MAX UNIT ns ns ns ns ns ns ns ns ns 75000 ns ns 75000 ns ns ns ns ns ns ns ns 75000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SYM/ALT. SYM tc(rd)/tRC tc(W) /tWC tc(rdW) /tRMW tc(P) /tPC tc(rdWP) /tPRMW tc(TRD) /tRC tc(TW) /tWC tc(SC) /tSCC t w(CH) /tCPN tw(CL)/tCAS t w(RH) /tRP tw(RL)/tRAS t w(WL) /tWP t w(TRG) t w(SCH) /tSC t w(SCL)/tSCP tw(SEL)/tSE t w(SEH) /tSEP t w(GH) /tTP t w(RL)P tsu(CA)/tASC tsu(SFC) /tFSC t su(RA)/tASR tsu(WMR) /tWSR t su(DQR) /tMS t su(TRG) /tTHS tsu(SE) /tESR t su(SESC) /tSWIS tsu(SFR) /tFSR t su(DCL)/tDSC tsu(DWL)/tDSW t su(rd)/tRCS t su(WCL)/tWCS tsu(WCH) /tCWL tsu(WRH) /tRWL
MIN 190 190 250 60 105 190 190 30 20 25 80 100 25 25 10 10 35 35 30 100 0 0 0 0 0 0 0 10 0 0 0 0 0 25 25
Cycle time, write
Cycle time, read-modify-write
Cycle time, page-mode read or write
Cycle time, page-mode read-modify-write Cycle time, read transfer
2 2
Cycle time, write transfer Cycle time, serial clock
2
Pulse duration, CAS\ high Pulse duration, CAS\ low
4
75000
30 90
Pulse duration, RAS\ high Pulse duration, RAS\ low Pulse duration,W\ low Pulse duration, TRG\ low Pulse duration, SC high Pulse duration, SC low Pulse duration, SE\ low Pulse duration, SE\ high Pulse duration, TRG\ high Pulse duration, RAS\ low (page mode) Setup time, column address Setup time, DSF before CAS\ low Setup time, row address Setup time, W\ before RAS\ low Setup time, DQ before RAS\ low Setup time, TRG\ before RAS\ low Setup time, SE\ before RAS\ low Setup time, serial write disable Setup time, DSF before RAS\ low Setup time, data before CAS\ low Setup time, data before W\ low Setup time, read command Setup time, early write command before CAS\ low Setup time, write before CAS\ high Setup time, write before RAS\ high with TRG\ = W\ = low
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
5
75000
120 25 30 12 12 40 40 20
75000
120 0 0 0 0 0 0 0 15 0 0 0 0 0 30 30
6
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
19
Austin Semiconductor, Inc. TIMING REQUIREMENTS (continued)1
-10 PARAMETER Setup time, SDQ before SC high Hold time, column address after CAS\ low Hold time, DSF after CAS\ low Hold time, row address after RAS\ low Hold time, TRG\ after RAS\ low Hold time, SE\ after RAS\ low with TRG\ = W\ = low Hold time, write mask, transfer enable after RAS\ low Hold time, DQ after RAS\ low (write-mask operation) Hold time, DSF after RAS\ low Hold time, column address after RAS\ low Hold time, data after CAS\ low Hold time, data after RAS\ low Hold time, data after W\ low Hold time, read after CAS\ high
8 8 7 7 6
SMJ44C251B MT42C4256
-12 MAX MIN 0 20 20 15 15 15 15 15 15 45 25 50 25 0 10 35 55 30 5 5 45 20 120 0 30 65 75 25 60 155 100 25 10 10 30 90 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
VRAM
SYM/ALT. SYM t su(SDS) /tSDS t h(CLCA)/tCAH t h(SFC) /tCFH t h(RA)/tRAH th(TRG) /tTLH th(SE) /tREH th(RWM) /tRWH th(RDQ) /tMH t h(SFR) /tRFH th(RLCA)/tAR t h(CLD) /tDH th(RLD) /tDHR th(WLD) /tDH th(CHrd)/tRCH th(RHrd)/tRRH t h(CLW) /tWCH th(RLW) /tWCR th(WLG) /tOEH t h(SDS) /tSDH t h(SHSQ) /tSOH t h(RSF) /tFHR t h(SCSE) /tSWIH t d(RLCH) /tCSH t d(CHRL)/tCRP t d(CLRH) /tRSH td(CLWL)/tCWD td(RLCL)/tRCD t d(CARH) /tRAL td(RLWL)/tRWD
10
MIN 0 20 20 15 15 15 15 15 15 45 20 45 20 0 10 30 50 25 5 5 45 20 100 0 25 55 25 50 130 85 25 10 10 25
Hold time, read after RAS\ high Hold time, write after CAS\ low Hold time, write after RAS\ low Hold time, TRG\ after W\ low
9
7
Hold time, SDQ after SC high Hold time, SDQ after SC high Hold time, DSF after RAS\ low Hold time, serial-write disable Delay time, RAS\ low to CAS\ high Delay time, CAS\ high to RAS\ low Delay time, CAS\ low to RAS\ high Delay time, CAS\ low to W\ low
10,11 12
Delay time, RAS\ low to CAS\ low
Delay time, column address to RAS\ high Delay time, RAS\ low to W\ low
10
Delay time, column address to W\ low Delay time, RAS\ low to CAS\ high Delay time, CAS\ low to RAS\ low
13
td(CAWL)/tAWD td(RLCH)RF/tCHR td(CLRL)RF/tCSR
13
13 td(RHCL)RF/tRPC Delay time, RAS\ high to CAS\ low Delay time, CAS\ low to TRG\ high for DRAM read td(CLGH) cycles
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
20
Austin Semiconductor, Inc. TIMING REQUIREMENTS (continued)1
-10 PARAMETER Delay time, TRG\ high before data applied at DQ Delay time, RAS\ low to TRG\ high (real-time-reload read-transfer cycle only) Delay time, RAS\ low to first SC high after TRG\ high Delay time, CAS\ low to first SC high after TRG\ high
14 14,15,16 15,16 14
SMJ44C251B MT42C4256
-12 MAX MIN 30 95 140 45 20 -10 20 20 30 tw(RH) 40 15 20 5 50 10 50 15 0 0 50 30 25 60 MAX UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
VRAM
SYM/ALT. SYM t d(GHD) /tOED td(RLTH) /tRTH td(RLSH) /tRSD td(CLSH) /tCSD td(SCTR) /tTSL td(THRH) /tTRD td(SCRL)/tSRS td(SCSE) td(RHSC) /tSRD
19
MIN 25 90 130 40 15 -10 10 20 25 tw(RH) 35 10 15 5 45 10 15 0 0 50 25 25
Delay time, SC high to TRG\ high
Delay time, TRG\ high to RAS\ high Delay time, SC high to RAS\ low with
6, 17, 18
TRG\ = W\ = low Delay time, SC high to SE\ high in serial-input mode Delay time, RAS\ high to SC high
6
Delay time, TRG\ high to RAS\ low Delay time, TRG\ high to SC high
20
td(THRL)/tTRP td(THSC) /tTSD td(SESC) /tSWS td(RHMS) td(CLGH) /tCTH td(CASH) /tASD td(CAGH) /tATH td(RLCA)/tRAD t d(DCL)/tDZC td(DGL)/tDZO td(RLSD) /tSDD t d(GLRH) /tROH td(MSRL)
15, 16
Delay time, SE\ low to SC high Delay time, RAS\ high to last (most significant) rising edge of SC before boundary switch during split-register read-transfer cycles Delay time, CAS\ low to TRG\ high in real-time read-transfer cycles Delay time, column address to first SC in earlyload read-transfer cycles Delay time, column address to TRG\ high in realtime read-transfer cycles Delay time, RAS\ low to column address Delay time, data to CAS\ low Delay time, data to TRG\ low Delay time, RAS\ low to serial-input data Delay time, TRG\ low to RAS\ high Delay time, last (most significant) rising edge of SC to RAS\ low before boundary switch during split-register read-transfer cycles Delay time, last (255 or 511) rising edge of SC to QSF switching a the boundary during split-register read transfer cycles Delay time, CAS\ low to QSF switching in readtransfer or write-transfer cycles Delay time, TRG\ high to QSF switching in readtransfer or write-transfer cycles Delay time, RAS\ low to QSF switching in readtransfer or write-transfer cycles Refresh time interval, memory Transition time
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
12
21
td(SCQSF) /tSQD
40
40
ns
21
td(CLQSF) /tCQD td(GHQSF) /tTQD td(RLQSF) /tRQD t rf /tREF t t/tT 3
35 30 75 8 50 3
35 30 75 8 50
ns ns ns ms ns
21
21
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21
Austin Semiconductor, Inc.
NOTES:
SMJ44C251B MT42C4256
VRAM
1. Timing measurements are referenced to VIL max and VIH min. 2. All cycle times assume tt = 5 ns. 3. When the odd tap is used (tap address can be 0-511, and odd taps are 1, 3, 5, etc.), the cycle time for SC in the first serial data out cycle needs to be 70 ns minimum. 4. In a read-modify-write cycle, td(CLWL) and tsu(WCH) must be observed. Depending on the user's transition times, this may require additional CAS\ low time [tw(CL) ]. 5. In a read-modify-write cycle, td(RLWL) and tsu(WRH) must be observed. Depending on the user's transition times, this may require additional RAS\ low time [tw(RL) ]. 6. Register-to-memory (write) transfer cycles only 7. The minimum value is measured when td(RLCL) is set to td(RLCL) min as a reference. 8. Either th(RHrd) or t(CHrd) must be satisfied for a read cycle. 9. Output-enable-controlled write. Output remains in the high-impedance state for the entire cycle. 10. Read-modify-write operation only 11. TRG\ must disable the output buffers prior to applying data to the DQ terminals. 12. The maximum value is specified only to assure RAS\ access time. 13. CAS\-before-RAS\ refresh operation only 14. Early-load read-transfer cycle only 15. Real-time-reload read-transfer cycle only 16. Late-load read-transfer cycle only 17. In a read-transfer cycle, the state of SC when RAS\ falls is a don't care condition. However, to assure proper sequencing of the internal clock circuitry, there can be no positive transitions of SC for at least 10 ns prior to when RAS\ goes low. 18. In a memory-to-register (read) transfer cycle, td(SCRL) applies only when the SAM was previously in serial-input mode. 19. Memory-to-register (read) and register-to-memory (write) transfer cycles only 20. Serial data-in cycles only 21. Switching times assume CL = 100 pF unless otherwise noted (see Figure 12).
FIGURE 12: LOAD CIRCUIT
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
22
Austin Semiconductor, Inc. FIGURE 13: Read-Cycle Timing
SMJ44C251B MT42C4256
VRAM
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
23
Austin Semiconductor, Inc. FIGURE 14: Early-Write-Cycle Timing
SMJ44C251B MT42C4256
VRAM
WRITE-CYCLE STATE TABLE
CYCLE Write Operation Write-mask load/use, Write DQs to I/Os Use previous write mask, Write DQs to I/Os Load write mask on later of W\ fall and CAS\ fall
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
1 L L H H
2 L L L L
STATE 3 4 H Don't Care L Write Mask L Don't Care H Don't Care
5 Valid Data Valid Data Valid Data Write Mask
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
24
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 15: Delayed-Write-Cycle Timing (Output-Enable-Controlled Write)
WRITE-CYCLE STATE TABLE
CYCLE Write Operation Write-mask load/use, Write DQs to I/Os Use previous write mask, Write DQs to I/Os Load write mask on later of W\ fall and CAS\ fall
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
1 L L H H
2 L L L L
STATE 3 4 H Don't Care L Write Mask L Don't Care H Don't Care
5 Valid Data Valid Data Valid Data Write Mask
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
25
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 16: Read-Write/Read-Modify-Write-Cycle Timing
WRITE-CYCLE STATE TABLE
CYCLE Write Operation Write-mask load/use, Write DQs to I/Os Use previous write mask, Write DQs to I/Os Load write mask on later of W\ fall and CAS\ fall
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
1 L L H H
2 L L L L
STATE 3 4 H Don't Care L Write Mask L Don't Care H Don't Care
5 Valid Data Valid Data Valid Data Write Mask
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
26
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 17: Enhanced-Page-Mode Read-Cycle Timing
NOTES:
1. Access time is ta(CP) or ta(CA) dependent. 2. Output can go from the high-impedance state to an invalid data state prior to the specified access time. NOTE A: A write cycle or a read-modify-write cycle can be mixed with the read cycles as long as the write and read-modify-write timing specifications are not violated and the proper polarity of DSF is selected on the falling edges of RAS\ and CAS\ to select the desired write mode (normal, block write, etc.)
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
27
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 18: Enhanced-Page-Mode Write-Cycle Timing
NOTES:
1. Referenced to CAS or W, whichever occurs last NOTE B: A read cycle or a read-modify-write cycle can be intermixed with write cycles, observing read and read-modify-write timing specifications. TRG\ must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late-write feature is used. If the early-writecycle timing is used, the state of TRG\ is a don't care after the minimum period th(TRG) from the falling edge of RAS\.
WRITE-CYCLE STATE TABLE
CYCLE Write Operation Write-mask load/use, Write DQs to I/Os Use previous write mask, Write DQs to I/Os Load write mask on later of W\ fall and CAS\ fall
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
1 L L H H
2 L L L L
STATE 3 4 H Don't Care L Write Mask L Don't Care H Don't Care
5 Valid Data Valid Data Valid Data Write Mask
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
28
Austin Semiconductor, Inc. FIGURE 19: Enhanced-Page-Mode Read-Modify-Write-Cycle Timing
SMJ44C251B MT42C4256
VRAM
NOTES:
1. Output can go from the high-impedance state to an invalid data state prior to the specified access time. NOTE C: A read or a write cycle can be intermixed with read-modify-write cycles as long as the read and write timing specifications are not violated.
WRITE-CYCLE STATE TABLE
CYCLE Write Operation Write-mask load/use, Write DQs to I/Os Use previous write mask, Write DQs to I/Os Load write mask on later of W\ fall and CAS\ fall
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
1 L L H H
2 L L L L
STATE 3 4 H Don't Care L Write Mask L Don't Care H Don't Care
5 Valid Data Valid Data Valid Data Write Mask
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
29
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 20: Load-Color-Register-Cycle Timing (Early-Write Load)
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
30
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 21: Load-Color-Register-Cycle Timing (Delayed-Write Load)
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
31
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 22: Block-Write-Cycle Timing (Early Write)
BLOCK-WRITE-CYCLE STATE TABLE
CYCLE Write-mask load/use, Block write Use previous write mask, Block write Write mask disable, Block write to all I/Os 1 L H L 2 L L H STATE 3 4 Write Mask Column Mask Don't Care Column Mask Don't Care Column Mask
Write mask data 0: I/O write disable 1: I/O write enable Column mask data DQn = 0 column write disable (n = 0, 1, 2, 3) 1 column write enable
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
DQ0 -- column 0 (address A1 = 0, A0 = 0) DQ1 -- column 1 (address A1 = 0, A0 = 1) DQ2 -- column 2 (address A1 = 1, A0 = 0) DQ3 -- column 3 (address A1 = 1, A0 = 1)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
32
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 23: Block-Write-Cycle Timing (Delayed-Write)
BLOCK-WRITE-CYCLE STATE TABLE
CYCLE Write-mask load/use, Block write Use previous write mask, Block write Write mask disable, Block write to all I/Os 1 L H L 2 L L H STATE 3 4 Write Mask Column Mask Don't Care Column Mask Don't Care Column Mask
Write mask data 0: I/O write disable 1: I/O write enable Column mask data DQn = 0 column write disable (n = 0, 1, 2, 3) 1 column write enable
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
DQ0 -- column 0 (address A1 = 0, A0 = 0) DQ1 -- column 1 (address A1 = 0, A0 = 1) DQ2 -- column 2 (address A1 = 1, A0 = 0) DQ3 -- column 3 (address A1 = 1, A0 = 1)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
33
Austin Semiconductor, Inc. FIGURE 24: Enhanced-Page-Mode Block-Write-Cycle Timing
SMJ44C251B MT42C4256
VRAM
NOTES:
1. Referenced to CAS\ or W\, whichever occurs last NOTE D: TRG\ must remain high throughout the entire page-mode operation to assure page-mode cycle time if the late write feature is used. If the early-write-cycle timing is used, the state of TRG\ is a don't care after the minimum period th(TRG) from the falling edge of RAS\.
ENHANCED-PAGE-MODE BLOCK-WRITE-CYCLE STATE TABLE
CYCLE Write-mask load/use, Block write Use previous write mask, Block write Write mask disable, Block write to all I/Os Write mask data 0: I/O write disable 1: I/O write enable Column mask data DQn = 0 column write disable (n = 0, 1, 2, 3) 1 column write enable
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
1 L H L
STATE 2 3 4 L Write Mask Column Mask L Don't Care Column Mask H Don't Care Column Mask DQ0 -- column 0 (address A1 = 0, A0 = 0) DQ1 -- column 1 (address A1 = 0, A0 = 1) DQ2 -- column 2 (address A1 = 1, A0 = 0) DQ3 -- column 3 (address A1 = 1, A0 = 1)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
34
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 25: RAS\-Only Refresh-Cycle Timing
NOTES:
NOTE E: In persistent write-per-bit function, W\ must be high at the falling edge of RAS\ during the refresh cycle.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
35
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 26: CBR-Refresh-Cycle Timing
NOTES:
NOTE F: In persistent write-per-bit operation, W\ must be high at the falling edge of RAS\ during the refresh cycle.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
36
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 27: Hidden-Refresh-Cycle Timing
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
37
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 28: Write-Mode-Control Pseudo-Transfer Timing
NOTES:
NOTE G: The write-mode-control cycle is used to change the SDQs from the output mode to the input mode. This allows serial data to be written into the data register. This figure assumes that the device was originally in the serial-read mode.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
38
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 29: Data-Register-to-Memory Transfer Timing, Serial Input Enable
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
39
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 30: Alternate Data-Register-to-Memory Transfer-Cycle Timing
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
40
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 31: Memory-to-Data-Register Transfer-Cycle Timing, Early-Load Operation
NOTES:
NOTE H: Early-load operation is defined as th(TRG) min < th(TRG) < td(RLTH) min. NOTE I: DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written from the 512 corresponding columns of the selected row. The data that is transferred into the data registers can be either shifted out or transferred back into another row. NOTE J: Once data is transferred into the data registers, the SAM is in the serial-read mode (i.e., SQ is enabled), allowing data to be shifted out of the registers. Also, the first bit to be read from the data register after TRG\ has gone high must be activated by a positive transition of SC.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
41
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 32: Memory-to-Data-Register Transfer-Cycle Timing, Real-Time-Reload Operation/Late-Load Operation
NOTES:
NOTE K: Late-load operation is defined as td(THRH) < 0 ns. NOTE L: DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written from the 512 corresponding columns of the selected row. The data that is transferred into the data registers can be either shifted out or transferred back into another row. NOTE M: Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing data to be shifted out of the registers. Also, the first bit to be read from the data register after TRG\ has gone high must be activated by a positive transition of SC.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
42
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 33: Memory-to-Data-Register Transfer-Cycle Timing, SDQ Ports Previously in Serial-Input Mode
NOTES:
NOTE N: Late-load operation is defined as td(THRH) < 0 ns. NOTE O: DQ outputs remain in the high-impedance state for the entire memory-to-data-register transfer cycle. The memory-to-data-register transfer cycle is used to load the data registers in parallel from the memory array. The 512 locations in each data register are written from the 512 corresponding columns of the selected row. The data that is transferred into the data registers may be either shifted out or transferred back into another row. NOTE P: Once data is transferred into the data registers, the SAM is in the serial read mode (i.e., SQ is enabled), allowing data to be shifted out of the registers. Also, the first bit to be read from the data register after TRG\ has gone high must be activated by a positive transition of SC.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
43
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 34: Split-Register-Mode Read-Transfer-Cycle Timing
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
44
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 35: Split-Register-Transfer Operating Sequence
NOTES:
NOTE Q: In order to achieve proper split-register operation, a normal read transfer should be performed before the first split-register transfer cycle. This is necessary to initialize the data register and the starting tap location. First serial access can then begin either after the normal read-transfer cycle (CASE I), during the first split-register cycle (CASE II), or even after the first split-register transfer cycle (CASE III). There is no minimum requirement of SC clock between the normal read-transfer cycle and the first split-register cycle. NOTE R: A split register transfer into the inactive half is not allowed until td(MSRL) is met. td(MSRL) is the minimum delay time between the rising edge of the serial clock of the last bit (bit 255 or 511) and the falling edge of RAS\ of the split-register transfer cycle into the inactive half. After td(MSRL) is met, the split-register transfer into the inactive half must also satisfy the td(RHMS) requirement. td(RHMS) is the minimum delay time between the rising edge of RAS\ of the split-register transfer cycle into the inactive half and the rising edge of the serial clock of the last bit (bit 255 or 511). There is a minimum requirement of one rising edge of SC clock between two split-register transfer cycles.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
45
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 36: Serial-Write-Cycle Timing (SE\ = VIL)
NOTES:
NOTE S: The serial data-in cycle is used to input serial data into the data registers. Before data can be written into the data registers via the SDQ terminals, the device must be put into the write mode by performing a write-mode-control (pseudo-transfer) cycle or any other write-transfer cycle. A read-transfer cycle is the only cycle that takes the serial port (SAM) out of the write mode and puts it into the read mode, disabling the input data. Data is written starting at the location specified by the input address loaded on the previous transfer cycle. NOTE T: While accessing data in the serial-data registers, the state of TRG\ is a don't care as long as TRG\ is held high when RAS\ goes low to prevent data transfers between memory and data registers.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
46
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 37: Serial-Write-Cycle Timing (SE\-Controlled Write)
NOTES:
NOTE U: The serial data-in cycle is used to input serial data into the data registers. Before data can be written into the data registers via the SDQ terminals, the device must be put into the write mode by performing a write-mode-control (pseudo-transfer) cycle or any other write-transfer cycle. A read-transfer cycle is the only cycle that takes the serial port (SAM) out of the write mode and puts it into the read mode, disabling the input data. Data is written starting at the location specified by the input address loaded on the previous transfer cycle. NOTE V: While accessing data in the serial-data registers, the state of TRG\ is a don't care as long as TRG\ is held high when RAS\ goes low to prevent data transfers between memory and data registers.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
47
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 38: Serial-Read-Cycle Timing (SE\ = VIL)
NOTES:
NOTE W: While reading data through the serial-data register, the state of TRG\ is a don't care as long as TRG\ is held high when RAS\ goes low. This is to avoid the initiation of a register-to-memory-to-register data-transfer operation. NOTE X: The serial data-out cycle is used to read data out of the data registers. Before data can be read via SDQ, the device must be put into the read mode by performing a transfer-read cycle. Any transfer-write cycles occurring between the transfer-read cycle and the subsequent shifting out of data take the device out of the read mode and put it in the write mode, not allowing the reading of data.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
48
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
FIGURE 39: Serial-Read-Cycle Timing (SE\-Controlled Read)
NOTES:
NOTE Y: While reading data through the serial-data register, the state of TRG\ is a don't care as long as TRG\ is held high when RAS\ goes low. This is to avoid the initiation of a register-to-memory-to-register data-transfer operation. NOTE Z: The serial data-out cycle is used to read data out of the data registers. Before data can be read via SDQ, the device must be put into the read mode by performing a transfer-read cycle. Any transfer-write cycles occurring between the transfer-read cycle and the subsequent shifting out of data take the device out of the read mode and put it in the write mode, not allowing the reading of data.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
49
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
MECHANICAL DEFINITIONS*
ASI Case #500 (Package Designator DCJ) SMD 5962-89497, Case Outline T
*All measurements are in inches.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
50
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
MECHANICAL DEFINITIONS*
ASI Case #109 (Package Designator C or JDM) SMD 5962-89497, Case Outline
X
*All measurements are in inches.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
51
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
MECHANICAL DEFINITIONS*
Package Designator HJM SMD 5962-89497, Case Outline Y
*All measurements are in inches.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
52
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
MECHANICAL DEFINITIONS*
ASI Case #203 (Package Designator EC or HMM) SMD 5962-89497, Case Outline Z
*All measurements are in inches.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
53
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
MECHANICAL DEFINITIONS*
Package Designator CZ or SVM SMD 5962-89497, Case Outline M
*All measurements are in inches.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
54
Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
MECHANICAL DEFINITIONS*
ASI Case #302 (Package Designator F) SMD 5962-89497, Case Outline U
SYMBOL A b c D E E1 E2 E3 e L Q S1
*All measurements are in inches.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
SMD SPECIFICATIONS MIN MAX 0.090 0.130 0.015 0.022 0.004 0.009 --0.740 0.380 0.420 --0.440 0.180 --0.030 --0.050 BSC 0.250 0.370 0.026 0.045 0.000 --Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
55
Austin Semiconductor, Inc. ORDERING INFORMATION
EXAMPLE: MT42C4256DCJ-10/XT Device Package Speed ns Process Number Type MT42C4256 DCJ -10 /* MT42C4256 DCJ -12 /* EXAMPLE: MT42C4256EC-10/883C Device Package Speed ns Process Number Type MT42C4256 EC -10 /* MT42C4256 EC -12 /* EXAMPLE: MT42C4256CZ-12/883C Device Package Speed ns Process Number Type MT42C4256 CZ -10 /* MT42C4256 CZ -12 /*
SMJ44C251B MT42C4256
VRAM
EXAMPLE: MT42C4256C-12/IT Device Package Speed ns Process Number Type MT42C4256 C -10 /* MT42C4256 C -12 /* EXAMPLE: MT42C4256F-12/XT Device Package Speed ns Process Number Type MT42C4256 F -10 /* MT42C4256 F -12 /*
EXAMPLE: SMJ44C251B 10HJM Device Package Speed ns Process Number Type SMJ44C251B 10 HJM See Note SMJ44C251B 12 HJM See Note EXAMPLE: SMJ44C251B 12HMM Device Package Process Speed ns Number Type SMJ44C251B 10 HMM See Note SMJ44C251B 12 HMM See Note
EXAMPLE: SMJ44C251B 12JDM Device Package Speed ns Process Number Type SMJ44C251B 10 JDM See Note SMJ44C251B 12 JDM See Note EXAMPLE: SMJ44C251B 10SVM Package Device Speed ns Process Type Number SMJ44C251B 10 SVM See Note SMJ44C251B 12 SVM See Note
*OPERATING TEMPERATURE XT = Military Temperature Range IT = Industrial Temperature Range 883C = MIL-STD-883C process
-55oC to +125oC -40C to +85C -55oC to +125oC
NOTE: SMJ prefix denotes MIL-STD-883C process, temperature range -55oC to +125oC.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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Austin Semiconductor, Inc.
SMJ44C251B MT42C4256
VRAM
ASI TO DSCC PART NUMBER CROSS REFERENCE*
Package Designator C or JDM ASI Part Number SMD Part Number MT42C4256C-10/883C 5962-8949704MXA MT42C4256C-12/883C 5962-8949703MXA SMJ44C251B-10JDM** 5962-8949704MXA SMJ44C251B-12JDM** 5962-8949703MXA Package Designator CZ or SVM ASI Part Number SMD Part Number MT42C4256CZ-10/883C 5962-8949704MMA MT42C4256CZ-12/883C 5962-8949703MMA SMJ44C251B-10SVM** 5962-8949704MMA SMJ44C251B-12SVM** 5962-8949703MMA
Package Designator EC or HMM SMD Part Number ASI Part Number MT42C4256EC-10/883C 5962-8949704MZA MT42C4256EC-12/883C 5962-8949703MZA SMJ44C251B-10HMM** 5962-8949704MZA SMJ44C251B-12HMM** 5962-8949703MZA
Package Designator DCJ ASI Part Number SMD Part Number MT42C4256DCJ-10/883C 5962-8949704MTA MT42C4256DCJ-12/883C 5962-8949703MTA
Package Designator F SMD Part Number ASI Part Number MT42C4256F-10/883C 5962-8949704MUA MT42C4256F-12/883C 5962-8949703MUA
Package Designator HJM ASI Part Number SMD Part Number SMJ44C251B-10HJM** 5962-8949704MYA SMJ44C251B-12HJM** 5962-8949703MYA
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD. ** Parts are listed on SMD under the old Texas Instruments part number. ASI purchased this product line in November of 1999.
SMJ44C251B/MT42C4256 Rev. 0.1 12/03
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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